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| Blackfin(R) Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory (see Memory Architecture on Page 4) Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring 0.8 V to 1.35 V core VDD with on-chip voltage regulator 2.5 V and 3.3 V compliant I/O 256-ball CSP_BGA (two sizes) and 297-ball PBGA package options Two internal memory-to-memory DMAs and one internal memory DMA controller 12 general-purpose 32-bit timers/counters with PWM capability SPI-compatible port UART with support for IrDA(R) Dual watchdog timers Dual 32-bit core timers 48 programmable flags (GPIO) On-chip phase-locked loop capable of 0.5x to 64x frequency multiplication Two parallel input/output peripheral interface units supporting ITU-R 656 video and glueless interface to analog front end ADCs Two dual channel, full duplex synchronous serial ports supporting eight stereo I2S channels PERIPHERALS Dual 12-channel DMA controllers (supporting 24 peripheral DMAs) Four memory-to-memory DMAs VOLTAGE REGULATOR IRQ CONTROL/ WATCHDOG TIMER JTAG TEST EMULATION IRQ CONTROL/ WATCHDOG TIMER B L1 INSTRUCTION MEMORY L1 DATA MEMORY B L1 INSTRUCTION MEMORY L1 DATA MEMORY L2 SRAM 128K BYTES UART IrDA SPI SPORT0 CORE SYSTEM/BUS INTERFACE IMDMA CONTROLLER SPORT1 EAB DMA CONTROLLER1 DMA CONTROLLER2 DAB 32 DAB EXTERNAL PORT FLASH/SDRAM CONTROL PPI0 PPI1 PAB 16 16 GPIO 32 TIMERS DEB BOOT ROM Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 3 Portable Low Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Watchdog Timer .................................................. 8 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ......................... 9 UART Port .......................................................... 9 Programmable Flags (PFx) .................................... 10 Parallel Peripheral Interface ................................... 10 Dynamic Power Management ................................ 11 Voltage Regulation .............................................. 12 Voltage Regulator Layout Guidelines .................... 12 Clock Signals ..................................................... 13 Booting Modes ................................................... 14 Instruction Set Description ................................... 14 Development Tools ............................................. 15 Designing an Emulator-Compatible Processor Board .. 16 Related Documents ............................................. 16 Pin Descriptions .................................................... 17 Specifications ........................................................ 20 Operating Conditions .......................................... 20 Electrical Characteristics ....................................... 20 Absolute Maximum Ratings .................................. 21 Package Information ........................................... 21 ESD Sensitivity ................................................... 21 Timing Specifications .......................................... 22 Clock and Reset Timing .................................... 23 Asynchronous Memory Read Cycle Timing ........... 24 Asynchronous Memory Write Cycle Timing .......... 25 SDRAM Interface Timing .................................. 26 External Port Bus Request and Grant Cycle Timing .. 27 Parallel Peripheral Interface Timing ..................... 28 Serial Ports ..................................................... 32 Serial Peripheral Interface (SPI) Port-- Master Timing ............................................. 35 Serial Peripheral Interface (SPI) Port-- Slave Timing ............................................... 36 Universal Asynchronous Receiver Transmitter (UART) Port--Receive and Transmit Timing ................. 37 Programmable Flags Cycle Timing ....................... 38 Timer Cycle Timing .......................................... 39 JTAG Test and Emulation Port Timing .................. 40 Output Drive Currents ......................................... 41 Power Dissipation ............................................... 42 Test Conditions .................................................. 42 Environmental Conditions .................................... 44 256-Ball CSP_BGA Ball Assignment ........................... 46 256-Ball CSP_BGA Ball Assignment ........................... 51 297-Ball PBGA ball assignment .................................. 56 Outline Dimensions ................................................ 61 Ordering Guide ..................................................... 64 REVISION HISTORY 4/07--Changes from Rev. A to Rev. B Added Text to Serial Ports (SPORTs) ............................. 9 Changed Font in Formula in Power Savings ...................12 Complete Rewrite of Operating Conditions ....................20 Complete Rewrite of Electrical Characteristics ................20 Edit to Figure Asynchronous Memory Read Cycle Timing .24 Edit to Figure Asynchronous Memory Write Cycle Timing 25 Deleted References to Temperature in Figures in Output Drive Currents ..........................................41 Moved Data to Operating Conditions and Rewrote Power Dissipation ..................................42 Deleted References to Temperature in Figures in Test Conditions ...................................................42 Added figures for 256-Ball CSP_BGA Ball Configuration (Top View) ....................................................................50 Added figure 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-4).............................................61 Added Models to Ordering Guide ................................64 5/06--Changes from Rev. 0 to Rev. A 1/05--Initial version Rev. B | Page 2 of 64 | June 2007 ADSP-BF561 GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of the Blackfin family of products targeting a variety of multimedia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors. These Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities in a single instruction set architecture. The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes: * 16K bytes of instruction SRAM/cache * 16K bytes of instruction SRAM * 32K bytes of data SRAM/cache * 32K bytes of data SRAM * 4K bytes of scratchpad SRAM Additional on-chip memory peripherals include: * 128K bytes of low latency on-chip L2 SRAM * Four-channel internal memory DMA controller * External memory controller with glueless support for SDRAM, mobile SDRAM, SRAM, and flash. The powerful 40-bit shifter has extensive capabilities for performing shifting, rotating, normalization, extraction, and depositing of data. The data for the computational units is found in a multiported register file of sixteen 16-bit entries or eight 32-bit entries. A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. Level 2 (L2) memories are other memories, on-chip or off-chip, that may take multiple processor cycles to access. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory space, holding both instructions and data. In addition, half of L1 instruction memory and half of L1 data memory may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and may protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the VisualDSP C/C++ compiler, resulting in fast and efficient software implementations. PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances. BLACKFIN PROCESSOR CORE As shown in Figure 2, each Blackfin core contains two multiplier/accumulators (MACs), two 40-bit ALUs, four video ALUs, and a single shifter. The computational units process 8-bit, 16-bit, or 32-bit data from the register file. Each MAC performs a 16-bit by 16-bit multiply in every cycle, with accumulation to a 40-bit result, providing eight bits of extended precision. The ALUs perform a standard set of arithmetic and logical operations. With two ALUs capable of operating on 16-bit or 32-bit data, the flexibility of the computation units covers the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be regarded as two 16-bit halves, so each ALU can accomplish very flexible single 16-bit arithmetic operations. By viewing the registers as pairs of 16-bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput. Rev. B | Page 3 of 64 | June 2007 ADSP-BF561 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 DA1 DA0 TO MEMORY 32 32 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 DAG1 DAG0 SP FP P5 P4 P3 P2 P1 P0 32 RAB 32 PREG SD LD1 LD0 32 32 32 32 32 ASTAT SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER 16 8 8 8 16 8 DECODE ALIGN 40 40 40 40 LOOP BUFFER A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core MEMORY ARCHITECTURE The ADSP-BF561 views memory as a single unified 4G byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency memory as cache or SRAM very close to the processor, and larger, lower cost and performance memory systems farther away from the processor. The ADSP-BF561 memory map is shown in Figure 3. The L1 memory system in each core is the highest performance memory available to each Blackfin core. The L2 memory provides additional capacity with lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of physical memory. The memory DMA controllers provide high bandwidth data movement capability. They can perform block transfers of code or data between the internal L1/L2 memories and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF561 has four blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory of each Blackfin core consisting of 16K bytes of four-way set-associative cache memory and 16K bytes of SRAM. The cache memory may also be configured as an SRAM. This memory is accessed at full processor speed. When configured as SRAM, each of the two 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The second on-chip memory block is the L1 data memory of each Blackfin core which consists of four banks of 16K bytes each. Two of the L1 data memory banks can be configured as one way of a two-way set-associative cache or as an SRAM. The other two banks are configured as SRAM. All banks are accessed at full processor speed. When configured as SRAM, each of the four 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The third memory block associated with each core is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM (it cannot be configured as cache memory and is not accessible via DMA). Rev. B | Page 4 of 64 | June 2007 ADSP-BF561 CORE A MEMORY MAP 0xFFFF FFFF 0xFFE0 0000 0xFFC0 0000 0xFFB0 1000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFFA0 4000 0xFFA0 0000 0xFF90 8000 0xFF90 4000 0xFF90 0000 0xFF80 8000 0xFF80 4000 0xFF80 0000 RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) 0xFEB2 0000 0xFEB0 0000 0xEF00 4000 0xEF00 0000 0x3000 0000 0x2C00 0000 0x2800 0000 0x2400 0000 0x2000 0000 Top of last SDRAM page RESERVED L2 SRAM (128K) RESERVED BOOT ROM RESERVED ASYNC MEMORY BANK 3 ASYNC MEMORY BANK 2 ASYNC MEMORY BANK 1 ASYNC MEMORY BANK 0 RESERVED SDRAM BANK 3 SDRAM BANK 2 SDRAM BANK 1 0x0000 0000 SDRAM BANK 0 EXTERNAL MEMORY 0xFF80 0000 0xFF70 1000 0xFF70 0000 0xFF61 4000 0xFF61 0000 0xFF60 4000 0xFF60 0000 0xFF50 8000 0xFF50 4000 0xFF50 0000 0xFF40 8000 0xFF40 4000 0xFF40 0000 INTERNAL MEMORY RESERVED CORE MMR REGISTERS CORE MMR REGISTERS SYSTEM MMR REGISTERS CORE B MEMORY MAP Figure 3. Memory Map The fourth on-chip memory system is the L2 SRAM memory array which provides 128K bytes of high speed SRAM operating at one half the frequency of the core, and slightly longer latency than the L1 memory banks. The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low latency 64-bit wide data path port into the L2 SRAM memory. Each Blackfin core processor has its own set of core Memory Mapped Registers (MMRs) but share the same system MMR registers and 128K bytes L2 SRAM memory. (SDRAM) as well as up to four banks of asynchronous memory devices, including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to four banks of SDRAM, with each bank containing between 16M bytes and 128M bytes providing access to up to 512M bytes of SDRAM. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. This allows flexible configuration and upgradability of system memory while allowing the core to view all SDRAM as a single, contiguous, physical address space. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a External (Off-Chip) Memory The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection to up to four banks of synchronous DRAM Rev. B | Page 5 of 64 | June 2007 ADSP-BF561 64M byte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64M bytes of memory. The ADSP-BF561 event controller consists of two stages: the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF561. Table 1 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 1. Core Event Controller (CEC) Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exceptions Global Enable Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 Booting The ADSP-BF561 contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF561 is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. Event Handling The event controller on the ADSP-BF561 handles all asynchronous and synchronous events to the processor. The ADSP-BF561 provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. * Reset - This event resets the processor. * Nonmaskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. * Exceptions - Events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. Conditions such as data alignment violations or undefined instructions cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, and an explicit software instruction. Each event has an associated register to hold the return address and an associated "return from event" instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. System Interrupt Controller (SIC) The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (SIC_IAR7-0). Table 2 describes the inputs into the SIC and the default mappings into the CEC. Rev. B | Page 6 of 64 | June 2007 ADSP-BF561 Table 2. System Interrupt Controller (SIC) Peripheral Interrupt Event PLL Wakeup DMA1 Error (Generic) DMA2 Error (Generic) IMDMA Error PPI0 Error PPI1 Error SPORT0 Error SPORT1 Error SPI Error UART Error Reserved DMA1 Channel 0 Interrupt (PPI0) DMA1 Channel 1 Interrupt (PPI1) DMA1 Channel 2 Interrupt DMA1 Channel 3 Interrupt DMA1 Channel 4 Interrupt DMA1 Channel 5 Interrupt DMA1 Channel 6 Interrupt DMA1 Channel 7 Interrupt DMA1 Channel 8 Interrupt DMA1 Channel 9 Interrupt DMA1 Channel 10 Interrupt DMA1 Channel 11 Interrupt DMA2 Channel 0 Interrupt (SPORT0 Rx) DMA2 Channel 1 Interrupt (SPORT0 Tx) DMA2 Channel 2 Interrupt (SPORT1 Rx) DMA2 Channel 3 Interrupt (SPORT1 Tx) DMA2 Channel 4 Interrupt (SPI) DMA2 Channel 5 Interrupt (UART Rx) DMA2 Channel 6 Interrupt (UART Tx) DMA2 Channel 7 Interrupt DMA2 Channel 8 Interrupt DMA2 Channel 9 Interrupt DMA2 Channel 10 Interrupt DMA2 Channel 11 Interrupt Timer0 Interrupt Timer1 Interrupt Timer2 Interrupt Timer3 Interrupt Timer4 Interrupt Timer5 Interrupt Timer6 Interrupt Timer7 Interrupt Timer8 Interrupt Timer9 Interrupt Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 Table 2. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event Timer10 Interrupt Timer11 Interrupt Programmable Flags 15-0 Interrupt A Programmable Flags 15-0 Interrupt B Programmable Flags 31-16 Interrupt A Programmable Flags 31-16 Interrupt B Programmable Flags 47-32 Interrupt A Programmable Flags 47-32 Interrupt B DMA1 Channel 12/13 Interrupt (Memory DMA/Stream 0) DMA1 Channel 14/15 Interrupt (Memory DMA/Stream 1) DMA2 Channel 12/13 Interrupt (Memory DMA/Stream 0) DMA2 Channel 14/15 Interrupt (Memory DMA/Stream 1) IMDMA Stream 0 Interrupt IMDMA Stream 1 Interrupt Watchdog Timer Interrupt Reserved Reserved Supplemental Interrupt 0 Supplemental Interrupt 1 Default Mapping IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG8 IVG8 IVG9 IVG9 IVG12 IVG12 IVG13 IVG7 IVG7 IVG7 IVG7 Event Control The ADSP-BF561 provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each of the registers is 16 bits wide, while each bit represents a particular event class. * CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but may also be written to clear (cancel) latched events. This register may be read while in supervisor mode and may only be written while in supervisor mode when the corresponding IMASK bit is cleared. * CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, thereby preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read from or written to while in supervisor mode. Rev. B | Page 7 of 64 | June 2007 ADSP-BF561 Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively. * CEC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing six 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 2. * SIC Interrupt Mask Registers (SIC_IMASKx) - These registers control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in these registers masks the peripheral event, thereby preventing the processor from servicing the event. * SIC Interrupt Status Registers (SIC_ISRx) - As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt; a cleared bit indicates the peripheral is not asserting the event. * SIC Interrupt Wakeup Enable Registers (SIC_IWRx) - By enabling the corresponding bit in these registers, each peripheral can be configured to wake up the processor, should the processor be in a powered-down mode when the event is generated. Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the mode of the processor. controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPIs. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF561 DMA controllers support both 1-dimensional (1-D) and 2-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the ADSP-BF561 DMA controllers include: * A single linear buffer that stops upon completion. * A circular autorefreshing buffer that interrupts on each full or fractionally full buffer. * 1-D or 2-D DMA using a linked list of descriptors. * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page. In addition to the dedicated peripheral DMA channels, each DMA Controller has four memory DMA channels provided for transfers between the various memories of the ADSP-BF561 system. These enable transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer mechanism. Further, the ADSP-BF561 has a four channel Internal Memory DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories. WATCHDOG TIMER Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog generated reset. DMA CONTROLLERS The ADSP-BF561 has two independent DMA controllers that support automated data transfers with minimal overhead for the DSP cores. DMA transfers can occur between the ADSP-BF561 internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory Rev. B | Page 8 of 64 | June 2007 ADSP-BF561 The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. An additional 250 mV of SPORT input hysteresis can be enabled by setting Bit 15 of the PLL_CTL register. When this bit is set, all SPORT input pins have the increased hysteresis. TIMERS There are 14 programmable timer units in the ADSP-BF561. Each of the 12 general-purpose timer units can be independently programmed as a Pulse Width Modulator (PWM), internally or externally clocked timer, or pulse width counter. The general-purpose timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel. The general-purpose timers can generate interrupts to the processor core providing periodic events for synchronization, either to the processor clock or to a count of external signals. In addition to the 12 general-purpose programmable timers, another timer is also provided for each core. These extra timers are clocked by the internal processor clock (CCLK) and are typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PERIPHERAL INTERFACE (SPI) PORT The ADSP-BF561 processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7-1) let the processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface which supports both master/slave modes and multimaster environments. The baud rate and clock phase/polarities for the SPI port are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI DMA controller can only service unidirectional accesses at any given time. The SPI port clock rate is calculated as: f SCLK SPI Clock Rate = ----------------------------------2 x SPI_BAUD Where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. SERIAL PORTS (SPORTs) The ADSP-BF561 incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other DSP components and shift registers for shifting data in and out of the data registers. * Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most significant bit first or least significant bit first. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The DSP can link or chain sequences of DMA transfers between a SPORT and memory. UART PORT The ADSP-BF561 processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: * PIO (programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. * DMA (direct memory access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated June 2007 Rev. B | Page 9 of 64 | ADSP-BF561 DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable. The UART programmable features include: * Supporting bit rates ranging from (fSCLK/1,048,576) bits per second to (fSCLK/16) bits per second. * Supporting data formats from seven bits to 12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port's clock rate is calculated as: f SCLK UART Clock Rate = ---------------------------------------------16 x UART_Divisor Where the 16-bit UART_Divisor comes from the UART_DLH register (most significant 8 bits) and UART_DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA) serial infrared physical layer link specification (SIR) protocol. interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be configured to generate software interrupts. * Flag interrupt sensitivity registers - These registers specify whether individual PFx pins are level- or edge-sensitive and specify, if edge-sensitive, whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge sensitivity. PARALLEL PERIPHERAL INTERFACE The ADSP-BF561 processor provides two parallel peripheral interfaces (PPI0, PPI1) that can connect directly to parallel A/D and D/A converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates at up to fSCLK/2 MHz, and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to 3 frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex, bi-directional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported. PROGRAMMABLE FLAGS (PFx) The ADSP-BF561 has 48 bidirectional, general-purpose I/O, programmable flag (PF47-0) pins. Some programmable flag pins are used by peripherals (see Pin Descriptions on Page 17). When not used as a peripheral pin, each programmable flag can be individually controlled by manipulation of the flag control, status, and interrupt registers as follows: * Flag direction control register - Specifies the direction of each individual PFx pin as input or output. * Flag control and status registers - Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a "write one to set" and "write one to clear" mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. Two control registers are provided, one register is written-to in order to set flag values, while another register is written-to in order to clear flag values. Reading the flag status register allows software to interrogate the sense of the flags. * Flag interrupt mask registers - These registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the flag control registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable an interrupt function, and the other flag interrupt mask register clears bits to disable an General-Purpose Mode Descriptions The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: * Input mode - frame syncs and data are inputs into the PPI. * Frame capture mode - frame syncs are outputs from the PPI, but data are inputs. * Output mode - frame syncs and data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit, and 10-bit through 16-bit data, and are programmable in the PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF561 processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Rev. B | Page 10 of 64 | June 2007 ADSP-BF561 Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling. ITU-R 656 Mode Descriptions The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct submodes are supported: * Active video only mode * Vertical blanking only mode * Entire field mode Table 3. Power Settings PLL Mode/State PLL Bypassed Full-On Enabled No Active Enabled/ Yes Disabled Sleep Enabled - Deep Sleep Disabled - Hibernate Disabled - Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power On On Disabled Enabled On Disabled Disabled On Disabled Disabled Off Active Operating Mode--Moderate Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 and L2 memories. In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes. Active Video Only Mode Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in the PPI_COUNT register). Sleep Operating Mode--High Dynamic Power Savings The sleep mode reduces power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event will wake up the processor. When in the sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). When in the sleep mode, system DMA access is only available to external memory, not to L1 or on-chip L2 memory. Vertical Blanking Interval Mode In this mode, the PPI only transfers vertical blanking interval (VBI) data. Entire Field Mode In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. Deep Sleep Operating Mode--Maximum Dynamic Power Savings The deep sleep mode maximizes power savings by disabling the clocks to the processor cores (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals will not be able to access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt (RESET). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled, the processor will transition to the active mode. DYNAMIC POWER MANAGEMENT The ADSP-BF561 provides four power management modes and one power management state, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF561 peripherals also reduces power consumption. See Table 3 for a summary of the power settings for each mode. Hibernate State--Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be Full-On Operating Mode--Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the default execution state in which maximum performance can be achieved. The processor cores and all enabled peripherals run at full speed. Rev. B | Page 11 of 64 | June 2007 ADSP-BF561 preserved. Since VDDEXT is still supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up by asserting the RESET pin. VOLTAGE REGULATION The ADSP-BF561 processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85 V to 1.30 V (within a specified tolerance, see Operating Conditions) from an external 2.25 V to 3.6 V supply. Figure 4 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (VDDEXT) supplied. While in the hibernate state, VDDEXT can still be applied, thus eliminating the need for external buffers. The voltage regulator can be activated from this power-down state by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user's discretion. The internal voltage regulation feature is not available on automotive grade models. External voltage regulation is required to ensure correct operation of these parts. Power Savings As shown in Table 4, the ADSP-BF561 supports two different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, the processor can take advantage of Dynamic Power Management, without affecting the I/O devices. There are no sequencing requirements for the various power domains. Table 4. ADSP-BF561 Power Domains Power Domain All internal logic I/O VDD Range VDDINT VDDEXT The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. The dynamic power management feature of the ADSP-BF561 allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The savings in power dissipation can be modeled using the power savings factor and % power savings calculations. The power savings factor is calculated as: power savings factor f CCLKRED V DDINTRED t RED = -------------------- x ------------------------- x ---------- f CCLKNOM V DDINTNOM t NOM where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage tNOM is the duration running at fCCLKNOM tRED is the duration running at fCCLKRED The percent power savings is calculated as: % power savings = ( 1 - power savings factor ) x 100% 2 2.25V TO 3.6V INPUT VOLTAGE RANGE VDDEXT (LOW-INDUCTANCE) SET OF DECOUPLING CAPACITORS + 100F 100nF + 100F FDS9431A 10F LOW ESR 100F ZHCS1000 10H VDDEXT VDDINT + VROUT SHORT AND LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. VROUT GND Figure 4. Voltage Regulator Circuit Voltage Regulator Layout Guidelines Regulator external component placement, board routing, and bypass capacitors all have a significant effect on noise injected into the other analog circuits on-chip. The VROUT1-0 traces and voltage regulator external components should be considered as noise sources when doing board layout and should not be routed or placed near sensitive circuits or components on the board. All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the ADSP-BF561 processors as possible. Rev. B | Page 12 of 64 | June 2007 ADSP-BF561 For further details on the on-chip voltage regulator and related board design guidelines, see the Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228) applications note on the Analog Devices web site (www.analog.com)--use site search on "EE-228". As shown in Figure 6, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user-programmable 0.5x to 64x multiplication factor. The default multiplier is 10x, but it can be modified by a software instruction sequence. On the fly frequency changes can be effected by simply writing to the PLL_DIV register. "FI NE " ADJ USTMENT RE QUI RE S PLL SEQ UENCING "CO ARSE " ADJUSTMENT ON-THE -FLY CLOCK SIGNALS The ADSP-BF561 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF561 processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 5. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in Figure 5 fine tune the phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 5 are typical values only. The capacitor values are dependent upon the crystal manufacturer's load capacitance recommendations and the physical PCB layout. The resistor value depends on the drive level specified by the crystal manufacturer. System designs should verify the customized values based on careful investigation on multiple devices over the allowed temperature range. A third-overtone crystal can be used at frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in Figure 5. / 1 , 2, 4, 8 CLKI N P LL 0.5 x TO 64 x CCLK VCO / 1 TO 15 SCLK SCLK CCLK SCLK 13 3MHz Figure 6. Frequency Modification Methods All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 5 illustrates typical system clock ratios. Table 5. Example System Clock Ratios Signal Name SSEL3-0 0001 0110 1010 Divider Ratio VCO/SCLK 1:1 6:1 10:1 Example Frequency Ratios (MHz) VCO SCLK 100 100 300 50 500 50 Blackfin CLKOUT TO PLL CIRCUITRY EN The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). CLKIN XTAL FOR OVERTONE OPERATION ONLY: 18pF* 18pF* NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. Figure 5. External Crystal Connections Rev. B | Page 13 of 64 | June 2007 ADSP-BF561 The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1-0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 6. This programmable core clock capability is useful for fast core frequency modifications. Table 6. Core Clock Ratios Signal Name CSEL1-0 00 01 10 11 Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1 Example Frequency Ratios (MHz) VCO CCLK 500 500 500 250 200 50 200 25 All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from SPI host device - The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor asserts a GPIO pin, called host wait (HWAIT), to signal the host device not to send any more bytes until the flag is deasserted. The flag is chosen by the user and this information is transferred to the Blackfin processor via bits 10:5 of the FLAG header. * Boot from SPI serial EEPROM (16-, 24-bit addressable) - The SPI uses the PF2 output pin to select a single SPI EPROM device, submits a read command at address 0x0000, and begins clocking data into the beginning of L1 instruction memory. A 16-, 24-bit addressable SPI-compatible EPROM must be used. For each of the boot modes, a boot loading protocol is used to transfer program and data blocks from an external memory device to their specified memory locations. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, Core A program execution commences from the start of L1 instruction SRAM (0xFFA0 0000). Core B remains in a heldoff state until Bit 5 of SICA_SYSCR is cleared by Core A. After that, Core B will start execution at address 0xFF60 0000. In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. The maximum PLL clock time when a change is programmed via the PLL_CTL register is 40 s. The maximum time to change the internal voltage via the internal voltage regulator is also 40 s. The reset value for the PLL_LOCKCNT register is 0x200. This value should be programmed to ensure a 40 s wakeup time when either the voltage is changed or a new MSEL value is programmed. The value should be programmed to ensure an 80 s wakeup time when both voltage and the MSEL value are changed. The time base for the PLL_LOCKCNT register is the period of CLKIN. BOOTING MODES The ADSP-BF561 has three mechanisms (listed in Table 7) for automatically loading internal L1 instruction memory, L2, or external memory after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. Table 7. Booting Modes BMODE1-0 Description 00 Execute from 16-bit external memory (Bypass Boot ROM) 01 Boot from 8-bit/16-bit flash 10 Boot from SPI host slave mode 11 Boot from SPI serial EEPROM (16-, 24-bit address range) INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax that was designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both a user (algorithm/application code) and a supervisor (O/S kernel, device drivers, debuggers, ISRs) mode of operation--allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. * A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU plus two load/store plus two pointer updates per cycle. The BMODE pins of the reset configuration register, sampled during power-on resets and software initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). Note that, in bypass mode, only Core A can execute instructions from external memory. * Boot from 8-bit/16-bit external flash memory - The 8-bit/16-bit flash boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. Rev. B | Page 14 of 64 | June 2007 ADSP-BF561 * All registers, I/O, and memory are mapped into a unified 4G byte memory space providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and kernel stack pointers. * Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits. * Set conditional breakpoints on registers, memory, and stacks. * Trace instruction execution. * Perform linear or statistical profiling of program execution. * Fill, dump, and graphically plot the contents of memory. * Perform source level debugging. * Create custom debugger windows. The VisualDSP++ IDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all development tools, including color syntax highlighting in the VisualDSP++ editor. These capabilities permit programmers to: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches. The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of embedded, real-time programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used with standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state when debugging an application that uses the VDK. The Expert Linker can be used to visually manipulate the placement of code and data in the embedded system. Memory utilization can be viewed in a color-coded graphical form. Code and data can be easily moved to different areas of the processor or external memory with the drag of the mouse. Runtime stack and heap usage can be examined. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides fullspeed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect the loading or timing of the target system. DEVELOPMENT TOOLS The ADSP-BF561 is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and the VisualDSP++(R) development environment. The same emulator hardware that supports other Analog Devices processors also fully emulates the ADSP-BF561. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to Blackfin assembly. The Blackfin processor has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information). * Insert breakpoints. CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. B | Page 15 of 64 | June 2007 ADSP-BF561 In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. EZ-KIT Lite Evaluation Board For evaluation of ADSP-BF561 processors, use the ADSP-BF561 EZ-KIT Lite(R) board available from Analog Devices. Order part number ADDS-BF561-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on the ADSP-BF561. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues, including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices website (www.analog.com)--use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF561 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: * Getting Started With Blackfin Processors * ADSP-BF561 Blackfin Processor Hardware Reference * ADSP-BF53x/BF56x Blackfin Processor Programming Reference * ADSP-BF561 Blackfin Processor Anomaly List Rev. B | Page 16 of 64 | June 2007 ADSP-BF561 PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in Table 8. In order to maintain maximum function and reduce package size and pin count, some pins have multiple functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. All pins are three-stated during and immediately after reset, with the exception of the external memory interface. On the external memory interface, the control and address lines are driven high during reset unless the BR pin is asserted. All I/O pins have their input buffers disabled, with the exception of the pins noted in the data sheet that need pull-ups or pulldowns if unused. Table 8. Pin Descriptions Pin Name EBIU ADDR25-2 DATA31-0 ABE3-0/SDQM3-0 BR BG BGH EBIU (ASYNC) AMS3-0 ARDY AOE AWE ARE EBIU (SDRAM) SRAS SCAS SWE SCKE SCLK0/CLKOUT SCLK1 SA10 SMS3-0 Type Function O I/O O I O O O I O O O O O O O O O O O Address Bus for Async/Sync Access Data Bus for Async/Sync Access Byte Enables/Data Masks for Async/Sync Access Bus Request (This pin should be pulled HIGH if not used.) Bus Grant Bus Grant Hang Bank Select Hardware Ready Control (This pin should be pulled HIGH if not used.) Output Enable Write Enable Read Enable Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Pin 0 Clock Output Pin 1 SDRAM A10 Pin Bank Select Driver Type1 A A A A A A A A A A A A A B B A A Rev. B | Page 17 of 64 | June 2007 ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name PF/SPI/TIMER PF0/SPISS/TMR0 PF1/SPISEL1/TMR1 PF2/SPISEL2/TMR2 PF3/SPISEL3/TMR3 PF4/SPISEL4/TMR4 PF5/SPISEL5/TMR5 PF6/SPISEL6/TMR6 PF7/SPISEL7/TMR7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15/EXT CLK PPI0 PPI0D15-8/PF47-40 PPI0D7-0 PPI0CLK PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 PPI0SYNC3 PPI1 PPI1D15-8/PF39-32 PPI1D7-0 PPI1CLK PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 PPI1SYNC3 SPORT0 RSCLK0/PF28 RFS0/PF19 DR0PRI DR0SEC/PF20 TSCLK0/PF29 TFS0/PF16 DT0PRI/PF18 DT0SEC/PF17 Type Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O Programmable Flag/Slave SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag/External Timer Clock Input PPI Data/Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync/Timer PPI Sync/Timer PPI Sync PPI Data/Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync/Timer PPI Sync/Timer PPI Sync Sport0 Receive Serial Clock/Programmable Flag Sport0 Receive Frame Sync/Programmable Flag Sport0 Receive Data Primary Sport0 Receive Data Secondary/Programmable Flag Sport0 Transmit Serial Clock/Programmable Flag Sport0 Transmit Frame Sync/Programmable Flag Sport0 Transmit Data Primary/Programmable Flag Sport0 Transmit Data Secondary/Programmable Flag Driver Type1 C C C C C C C C C C C C C C C C C C C C C C C C C C D C C D C C C Rev. B | Page 18 of 64 | June 2007 ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name SPORT1 RSCLK1/PF30 RFS1/PF24 DR1PRI DR1SEC/PF25 TSCLK1/PF31 TFS1/PF21 DT1PRI/PF23 DT1SEC/PF22 SPI MOSI MISO SCK UART RX/PF27 TX/PF26 JTAG EMU TCK TDO TDI TMS TRST Clock CLKIN XTAL Mode Controls RESET NMI0 NMI1 BMODE1-0 SLEEP BYPASS Voltage Regulator VROUT1-0 Supplies VDDEXT VDDINT GND No Connection 1 Type Function I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O I I I I O I I I I O I O P P G NC Sport1 Receive Serial Clock/Programmable Flag Sport1 Receive Frame Sync/Programmable Flag Sport1 Receive Data Primary Sport1 Receive Data Secondary/Programmable Flag Sport1 Transmit Serial Clock/Programmable Flag Sport1 Transmit Frame Sync/Programmable Flag Sport1 Transmit Data Primary/Programmable Flag Sport1 Transmit Data Secondary/Programmable Flag Master Out Slave In Master In Slave Out (This pin should be pulled HIGH through a 4.7 k resistor if booting via the SPI port.) SPI Clock UART Receive/Programmable Flag UART Transmit/Programmable Flag Emulation Output JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset (This pin should be pulled LOW if JTAG is not used.) Clock/Crystal Input (This pin needs to be at a level or clocking.) Crystal Connection Reset (This pin is always active during core power-on.) Nonmaskable Interrupt Core A (This pin should be pulled LOW when not used.) Nonmaskable Interrupt Core B (This pin should be pulled LOW when not used.) Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.) Sleep PLL BYPASS Control (Pull-up or pull-down Required.) External FET Drive Power Supply Power Supply Power Supply Return NC Driver Type1 D C C D C C C C C D C C C C C Refer to Figure 28 on Page 41 to Figure 32 on Page 42. Rev. B | Page 19 of 64 | June 2007 ADSP-BF561 SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter VDDINT Internal Supply Voltage1 VDDINT VDDINT VDDEXT VDDEXT VIH VIL TJ TJ TJ TJ TJ 1 2 Internal Supply Voltage1 Internal Supply Voltage3 External Supply Voltage External Supply Voltage High Level Input Voltage4, 5 Low Level Input Voltage5 Junction Temperature Junction Temperature Junction Temperature Junction Temperature Junction Temperature Conditions Nonautomotive 500 MHz and 533 MHz speed grade models and ADSP-BF561SKBCZ6002 600 MHz speed grade models except ADSP-BF561SKBCZ6002 Automotive grade models2 Nonautomotive grade models2 Automotive grade models2 Min 0.8 0.8 0.95 2.25 2.7 2.0 -0.3 0 0 -40 0 -40 Nominal Max 1.25 1.375 1.35 1.25 2.5 or 3.3 3.3 1.4185 1.312 3.6 3.6 3.6 +0.6 +105 +95 +115 +95 +115 Unit V V V V V V V C C C C C 256-Ball CSP_BGA (12 mm 12 mm) @ TAMBIENT = 0C to +70C 256-Ball CSP_BGA (17 mm 17 mm) @ TAMBIENT = 0C to +70C 256-Ball CSP_BGA (17 mm 17 mm) @ TAMBIENT =-40C to +85C 297-Ball PBGA @ TAMBIENT = 0C to +70C 297-Ball PBGA @ TAMBIENT = -40C to +85C Internal voltage (VDDINT) regulator tolerance is -5% to +10% for all models except 600 MHz models in the PBGA package where tolerance is -7% to +12% See Ordering Guide on Page 64. 3 The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation. 4 The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional and input only pins. 5 Applies to all signal pins. ELECTRICAL CHARACTERISTICS Parameter VOH VOL IIH IIHP IIL4 IOZH IOZL4 CIN IDDHIBERNATE IDDDEEPSLEEP8 IDD_TYP8, 9 IDD_TYP8, 9 IDD_TYP8, 9 1 2 High Level Output Voltage1 Low Level Output Voltage1 High Level Input Current2 High Level Input Current JTAG3 Low Level Input Current2 Three-State Leakage Current5 Three-State Leakage Current5 Input Capacitance6 VDDINT Current in Hibernate Mode VDDINT Current in Deep Sleep Mode VDDINT Current VDDINT Current VDDINT Current Test Conditions VDDEXT = 3.0 V, IOH = -0.5 mA VDDEXT = 3.0 V, IOL = 2.0 mA VDDEXT = Maximum, VIN = VDD Maximum VDDEXT = Maximum, VIN = VDD Maximum VDDEXT = Maximum, VIN = 0 V VDDEXT = Maximum, VIN = VDD Maximum VDDEXT = Maximum, VIN = 0 V fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V VDDEXT = 3.65 V with Voltage Regulator Off (VDDINT = 0 V) VDDINT = 0.8 V, TJUNCTION = 25C VDDINT = 0.8 V, fIN = 50 MHz, TJUNCTION = 25C VDDINT = 1.25 V, fIN = 500 MHz, TJUNCTION = 25C VDDINT = 1.35 V, fIN = 600 MHz, TJUNCTION = 25C Min 2.4 Typical Max 0.4 10.0 50.0 10.0 10.0 10.0 87 4 50 32 66 469 588 Unit V V A A A A A pF A mA mA mA mA Applies to output and bidirectional pins. Applies to input pins except JTAG inputs. 3 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 4 Absolute value. 5 Applies to three-statable pins. 6 Applies to all signal pins. 7 Guaranteed, but not tested. 8 See Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)--use site search on "EE-293". 9 Processor executing 75% dual MAC, 25% ADD with moderate data bus activity. Rev. B | Page 20 of 64 | June 2007 ADSP-BF561 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1 Output Voltage Swing Load Capacitance2 Storage Temperature Range Junction Temperature Under Bias 1 2 PACKAGE INFORMATION The information presented in Figure 7 and Table 10 provides details about the package branding for the Blackfin processors. For a complete listing of product availability, see the Ordering Guide on Page 64. Value -0.3 V to +1.42 V -0.5 V to +3.8 V -0.5 V to +3.8 V -0.5 V to VDDEXT + 0.5 V 200 pF -65 C to +150 C 125 C a ADSP-BF561 tppZccc vvvvvv.x n.n yyww country_of_origin B Figure 7. Product Information on Package Applies to 100% transient duty cycle. For other duty cycles see Table 9. For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS. Table 10. Package Brand Information Brand Key t pp Z ccc vvvvvv.x n.n yyww Field Description Temperature Range Package Type RoHS Compliant Part See Ordering Guide Assembly Lot Code Silicon Revision Date Code Table 9. Maximum Duty Cycle for Input Transient Voltage1 VIN Min (V) -0.50 -0.70 -0.80 -0.90 -1.00 1 2 VIN Max (V)2 3.80 4.00 4.10 4.20 4.30 Maximum Duty Cycle 100% 40% 25% 15% 10% Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1-0. Only one of the listed options can apply to a particular design. ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be take to avoid performance degradation or loss of functionality. Rev. B | Page 21 of 64 | June 2007 ADSP-BF561 TIMING SPECIFICATIONS Table 11 through Table 13 describe the timing requirements for the ADSP-BF561 clocks (tCCLK = 1/fCCLK). Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock, and Voltage Controlled Oscillator (VCO) operating frequencies, as described in Absolute Maximum Ratings on Page 21. Table 14 describes phase-locked loop operating conditions. Table 11. Core Clock (CCLK) Requirements--500 MHz and 533 MHz Speed Grade Models1 Parameter fCCLK CCLK Frequency (VDDINT = 1.25 Vminimum)2, 3 fCCLK CCLK Frequency (VDDINT = 1.1875 Vminimum) fCCLK CCLK Frequency (VDDINT = 1.045 Vminimum) fCCLK CCLK Frequency (VDDINT = 0.95 Vminimum) fCCLK CCLK Frequency (VDDINT = 0.855 Vminimum)3, 4 CCLK Frequency (VDDINT = 0.8 V minimum)4 fCCLK 1 2 Max 533 500 444 350 300 250 Unit MHz MHz MHz MHz MHz MHz See Ordering Guide on Page 64. External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 64) to ensure correct operation. 3 Not applicable to nonautomotive grade models. See Ordering Guide on Page 64. 4 Not applicable to automotive grade models in PBGA package. See Ordering Guide on Page 64. Table 12. Core Clock (CCLK) Requirements--600 MHz Speed Grade Models in CSP_BGA Package1 Parameter fCCLK CCLK Frequency (VDDINT = 1.1875 V minimum) fCCLK CCLK Frequency (VDDINT = 1.045 V minimum) CCLK Frequency (VDDINT = 0.95 V minimum) fCCLK fCCLK CCLK Frequency (VDDINT = 0.855 V minimum) fCCLK CCLK Frequency (VDDINT = 0.8 V minimum) 1 Max 600 475 425 375 250 Unit MHz MHz MHz MHz MHz See Ordering Guide on Page 64. Table 13. Core Clock (CCLK) Requirements--600 MHz Speed Grade Models in PBGA Package1 Parameter fCCLK CCLK Frequency (VDDINT = 1.2825 V minimum)2 CCLK Frequency (VDDINT = 1.1875 V minimum) fCCLK fCCLK CCLK Frequency (VDDINT = 1.045 V minimum) fCCLK CCLK Frequency (VDDINT = 0.95 V minimum) fCCLK CCLK Frequency (VDDINT = 0.855 V minimum) fCCLK CCLK Frequency (VDDINT = 0.8 V minimum) 1 2 Max 600 500 444 350 300 250 Unit MHz MHz MHz MHz MHz MHz See Ordering Guide on Page 64. External voltage regulator required to ensure proper operation at 600 MHz 1.35 V nominal. Table 14. Phase-Locked Loop Operating Conditions Parameter Voltage Controlled Oscillator (VCO) Frequency Min 50 Max Maximum fCCLK Unit MHz Table 15. System Clock (SCLK) Requirements Parameter1 fSCLK fSCLK 1 CLKOUT/SCLK Frequency (VDDINT 1.14 V) CLKOUT/SCLK Frequency (VDDINT < 1.14 V) Max VDDEXT = 2.5 V/3.3 V 133 100 Unit MHz MHz tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK. Rev. B | Page 22 of 64 | June 2007 ADSP-BF561 Clock and Reset Timing Table 16 and Figure 8 describe clock and reset operations. Per Absolute Maximum Ratings on Page 21, combinations of CLKIN and clock multipliers must not result in core/system clocks exceeding the maximum limits allowed for the processor, including system clock restrictions related to supply voltage. Table 16. Clock and Reset Timing Parameter Timing Requirements tCKIN CLKIN (to PLL) Period1, 2, 3 tCKINL CLKIN Low Pulse CLKIN High Pulse tCKINH tWRST RESET Asserted Pulse Width Low4 1 2 Min 25.0 10.0 10.0 11 x tCKIN Max 100.0 Unit ns ns ns ns If DF bit in PLL_CTL register is set tCLKIN is divided by two before going to PLL, then the tCLKIN maximum period is 50 ns and the tCLKIN minimum period is 12.5 ns. Applies to PLL bypass mode and PLL nonbypass mode. 3 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 11 on Page 22 through Table 15 on Page 22. 4 Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including startup time of external clock oscillator). tCKIN CLKIN tCKINL RESET tCKINH tWRST Figure 8. Clock and Reset Timing Rev. B | Page 23 of 64 | June 2007 ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 17. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA31-0 Setup Before CLKOUT tHDAT DATA31-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min 2.1 0.8 4.0 0.0 Max Unit ns ns ns ns 6.0 0.8 ns ns Output pins include AMS3-0, ABE3-0, ADDR25-2, AOE, ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE CLKOUT t DO AMSx t HO ABE1-0 ADDR19-1 ABE, ADDRESS AOE t DO ARE tHO t SARDY ARDY tHARDY t HARDY t SARDY t SDAT t HDAT DATA15-0 READ Figure 9. Asynchronous Memory Read Cycle Timing Rev. B | Page 24 of 64 | June 2007 ADSP-BF561 Asynchronous Memory Write Cycle Timing Table 18. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA31-0 Disable After CLKOUT DATA31-0 Enable After CLKOUT tENDAT tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min 4.0 0.0 Max Unit ns ns 6.0 1.0 6.0 0.8 ns ns ns ns Output pins include AMS3-0, ABE3-0, ADDR25-2, DATA31-0, AOE, AWE. SETUP 2 CYCLES PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED 1 CYCLE HOLD 1 CYCLE CLKOUT t DO AMSx t HO ABE1-0 ADDR19-1 ABE, ADDRESS tDO AWE tHO t SARDY ARDY t HARDY t END AT DATA15-0 WRITE DATA tSARDY t DD AT Figure 10. Asynchronous Memory Write Cycle Timing Rev. B | Page 25 of 64 | June 2007 ADSP-BF561 SDRAM Interface Timing Table 19. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tSCLK CLKOUT Period1 CLKOUT Width High tSCLKH tSCLKL CLKOUT Width Low tDCAD Command, ADDR, Data Delay After CLKOUT2 tHCAD Command, ADDR, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 2 Min 1.5 0.8 7.5 2.5 2.5 Max Unit ns ns ns ns ns ns ns ns ns 4.0 0.8 4.0 1.0 Refer to Table 15 on Page 22 for maximum fSCLK at various VDDINT. Command pins include: SRAS, SCAS, SWE, SDQM, SMS3-0, SA10, SCKE. tSCLK CLKOUT tSCLKH t SSDAT tHSDAT DATA (IN) t SCLKL t DCAD tENSDAT DATA(OUT) tD SDA T tHCAD tDCAD CMND ADDR (OUT) tHCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 11. SDRAM Interface Timing Rev. B | Page 26 of 64 | June 2007 ADSP-BF561 External Port Bus Request and Grant Cycle Timing Table 20 and Figure 12 describe external port bus request and bus grant operations. Table 20. External Port Bus Request and Grant Cycle Timing Parameter1, 2 Timing Requirements tBS BR Asserted to CLKOUT High Setup tBH CLKOUT High to BR Deasserted Hold Time Switching Characteristics tSD CLKOUT Low to AMSx, Address and ARE/AWE Disable tSE CLKOUT Low to AMSx, Address and ARE/AWE Enable tDBG CLKOUT High to BG Asserted Setup tEBG CLKOUT High to BG Deasserted Hold Time tDBH CLKOUT High to BGH Asserted Setup CLKOUT High to BGH Deasserted Hold Time tEBH 1 2 Min 4.6 0.0 Max Unit ns ns 4.5 4.5 3.6 3.6 3.6 3.6 ns ns ns ns ns ns These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF. CLKOUT tBS BR tBH tSD tSE AMSx tSD tSE ADDR25-2 ABE3-0 tSD tSE AWE ARE tDBG BG tEBG tDBH BGH tEBH Figure 12. External Port Bus Request and Grant Cycle Timing Rev. B | Page 27 of 64 | June 2007 ADSP-BF561 Parallel Peripheral Interface Timing Table 21, and Figure 13 through Figure 16 on Page 30, describe default Parallel Peripheral Interface operations. Table 21. Parallel Peripheral Interface Timing Parameter Timing Requirements tPCLKW PPIxCLK Width1 tPCLK PPIxCLK Period1 External Frame Sync Setup Before PPIxCLK tSFSPE tHFSPE External Frame Sync Hold After PPIxCLK tSDRPE Receive Data Setup Before PPIxCLK tHDRPE Receive Data Hold After PPIxCLK Switching Characteristics tDFSPE Internal Frame Sync Delay After PPIxCLK Internal Frame Sync Hold After PPIxCLK tHOFSPE tDDTPE Transmit Data Delay After PPIxCLK tHDTPE Transmit Data Hold After PPIxCLK 1 If bit 4 of the PLL_CTL register is set, then Figure 17 on Page 30 and Figure 18 on Page 31 apply. Min 5.0 13.3 4.0 1.0 3.5 2.0 Max Unit ns ns ns ns ns ns 8.0 1.7 8.0 2.0 ns ns ns ns For PPI modes that use an internally generated frame sync, the PPIxCLK frequency cannot exceed fSCLK/2. For modes with no frame syncs or external frame syncs, PPIxCLK cannot exceed 75 MHz and fSCLK should be equal to or greater than PPIxCLK. FRAME SYNC IS DRIVEN OUT POLC = 0 PPIxCLK DATA0 IS SAMPLED PPIxCLK POLC = 1 tDFSPE t POLS = 1 PPIxSYNC11 POLS = 0 HOFSPE POLS = 1 PPIxSYNC2 POLS = 0 tSDRPE tHDRPE PPIxDATA Figure 13. PPI GP Rx Mode with Internal Frame Sync Timing (Default) Rev. B | Page 28 of 64 | June 2007 ADSP-BF561 FRAME SYNC IS SAMPLED FOR DATA0 DATA0 IS SAMPLED PPIxCLK POLC = 0 PPIxCLK POLC = 1 DATA1 IS SAMPLED t tSFSPE POLS = 1 PPIxSYNC1 POLS = 0 HFSPE POLS = 1 PPIxSYNC2 POLS = 0 t SDRPE t HDRPE PPIx_DATA Figure 14. PPI GP Rx Mode with External Frame Sync Timing (Default) FRAME SYNC IS DRIVEN OUT DATA0 IS DRIVEN OUT PPIxCLK POLC = 0 PPIxCLK POLC = 1 t tHOFSPE POLS = 1 PPIxSYNC1 POLS = 0 DFSPE POLS = 1 PPIxSYNC2 POLS = 0 t DDTPE tHDTPE PPIx_DATA DATA0 Figure 15. PPI GP Tx Mode with Internal Frame Sync Timing (Default) Rev. B | Page 29 of 64 | June 2007 ADSP-BF561 FRAME SYNC IS SAMPLED PPIxCLK POLC = 0 PPIxCLK POLC = 1 tHFSPE t POLS = 1 PPxSYNC1 POLS = 0 SFSPE DATA0 IS DRIVEN OUT POLS = 1 PPIxSYNC2 POLS = 0 t HDTPE PPIx_DATA DATA0 tDDTPE Figure 16. PPI GP Tx Mode with External Frame Sync Timing (Default) DATA SAMPLING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC = 0 PPIxCLK POLC = 1 DATA SAMPLING/ FRAME SYNC SAMPLING EDGE tSFSPE POLS = 1 PPIxSYNC1 POLS = 0 t HFSPE POLS = 1 PPIxSYNC2 POLS = 0 tSDRPE PPIx_ ATA D tHDRPE Figure 17. PPI GP Rx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set) Rev. B | Page 30 of 64 | June 2007 ADSP-BF561 DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC = 0 PPIxCLK POLC = 1 t t POLS = 1 PPIxSYNC1 POLS = 0 SFSPE HFSPE DATA DRIVING/ FRAME SYNC SAMPLING EDGE POLS = 1 PPIxSYNC2 POLS = 0 tDDTPE t PPIx_ ATA D HDTPE Figure 18. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set) Rev. B | Page 31 of 64 | June 2007 ADSP-BF561 Serial Ports Table 22 through Table 25 on Page 34 and Figure 19 on Page 33 through Figure 20 on Page 34 describe Serial Port operations. Table 22. Serial Ports--External Clock Parameter Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRE Receive Data Setup Before RSCLKx1 tHDRE Receive Data Hold After RSCLKx1 tSCLKW TSCLKx/RSCLKx Width tSCLK TSCLKx/RSCLKx Period Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTE Transmit Data Delay After TSCLKx2 tHDTE Transmit Data Hold After TSCLKx2 1 2 Min 3.0 3.0 3.0 3.0 4.5 15.0 Max Unit ns ns ns ns ns ns 10.0 0.0 10.0 0.0 ns ns ns ns Referenced to sample edge. Referenced to drive edge. Table 23. Serial Ports--Internal Clock Parameter Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 Receive Data Setup Before RSCLKx1 tSDRI tHDRI Receive Data Hold After RSCLKx1 tSCLKW TSCLKx/RSCLKx Width tSCLK TSCLKx/RSCLKx Period Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTI Transmit Data Delay After TSCLKx2 tHDTI Transmit Data Hold After TSCLKx2 tSCLKIW TSCLKx/RSCLKx Width 1 2 Min 8.0 -2.0 6.0 0.0 4.5 15.0 Max Unit ns ns ns ns ns ns 3.0 -1.0 3.0 -2.0 4.5 ns ns ns ns ns Referenced to sample edge. Referenced to drive edge. Rev. B | Page 32 of 64 | June 2007 ADSP-BF561 DATA RECEIVE--INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE--EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW RSCLKx RSCLKx tSCLKEW tDFSI tHOFSI RFSx tDFSE tSFSI tHFSI RFSx tHOFSE tSFSE tHFSE tSDRI DRx tHDRI DRx tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT--INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT--EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW TSCLKx TSCLKx tSCLKEW tDFSI tHOFSI TFSx tDFSE tSFSI tHFSI TFSx tHOFSE tSFSE tHFSE tDDTI tHDTI DTx DTx tDDTE tHDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE. Figure 19. Serial Ports Rev. B | Page 33 of 64 | June 2007 ADSP-BF561 Table 24. Serial Ports--Enable and Three-State Parameter Switching Characteristics Data Enable Delay from External TSCLKx1 tDTENE tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1 1 Min 0 Max Unit ns ns ns ns 10.0 -2.0 3.0 Referenced to drive edge. Table 25. External Late Frame Sync Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 01, 2 tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01, 2 1 2 Min Max 10.0 Unit ns ns 0 MCE = 1, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE. If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply. EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE RSCLKx SAMPLE DRIVE tSFSE/I tHOFSE/I RFSx tDTENLFS tDDTTE/I tDTENE/I 1ST BIT 2ND BIT DTx tDDTLFSE LATE EXTERNAL TFS DRIVE TSCLKx SAMPLE DRIVE tSFSE/I tHOFSE/I TFSx tDTENLFS DTx tDDTTE/I tDTENE/I 1ST BIT 2ND BIT tDDTLFSE Figure 20. External Late Frame Sync Rev. B | Page 34 of 64 | June 2007 ADSP-BF561 Serial Peripheral Interface (SPI) Port-- Master Timing Table 26 and Figure 21 describe SPI port master operations. Table 26. Serial Peripheral Interface (SPI) Port--Master Timing Parameter Timing Requirements Data Input Valid to SCK Edge (Data Input Setup) tSSPIDM tHSPIDM SCK Sampling Edge to Data Input Invalid Switching Characteristics tSDSCIM SPISELx Low to First SCK Edge tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period Serial Clock Period tSPICLK tHDSM Last SCK Edge to SPISELx High tSPITDM Sequential Transfer Delay tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) Min 7.5 -1.5 2tSCLK - 1.5 2tSCLK - 0.5 2tSCLK - 1.5 4tSCLK - 1.5 2tSCLK - 1.5 2tSCLK - 1.5 0 -1.0 Max Unit ns ns ns ns ns ns ns ns ns ns 6 +4.0 SPISELx (OUTPUT) tSDSCIM SCK (CPOL = 0) (OUTPUT) tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tSPICLM SCK (CPOL = 1) (OUTPUT) tSPICHM tDDSPIDM MOSI (OUTPUT) CPHA=1 MISO (INPUT) MSB tHDSPIDM LSB tSSPIDM MSB VALID tHSPIDM tSSPIDM LSB VALID tHSPIDM tDDSPIDM MOSI (OUTPUT) CPHA=0 MISO (INPUT) MSB tHDSPIDM LSB tSSPIDM MSB VALID tHSPIDM LSB VALID Figure 21. Serial Peripheral Interface (SPI) Port--Master Timing Rev. B | Page 35 of 64 | June 2007 ADSP-BF561 Serial Peripheral Interface (SPI) Port-- Slave Timing Table 27 and Figure 22 describe SPI port slave operations. Table 27. Serial Peripheral Interface (SPI) Port--Slave Timing Parameter Timing Requirements Serial Clock High Period tSPICHS tSPICLS Serial Clock Low Period tSPICLK Serial Clock Period tHDS Last SCK Edge to SPISS Not Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion to First SCK Edge Data Input Valid to SCK Edge (Data Input Setup) tSSPID tHSPID SCK Sampling Edge to Data Input Invalid Switching Characteristics tDSOE SPISS Assertion to Data Out Active tDSDHI SPISS Deassertion to Data High Impedance tDDSPID SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold) tHDSPID Min 2tSCLK - 1.5 2tSCLK - 1.5 4tSCLK - 1.5 2tSCLK - 1.5 2tSCLK - 1.5 2tSCLK - 1.5 1.6 1.6 0 0 0 0 8 8 10 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns SPISS (INPUT) tSPICHS SCK (CPOL = 0) (INPUT) tSPICLS tSPICLK tHDS tSPITDS tSDSCI SCK (CPOL = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPID tHDSPID tDDSPID tDSDHI LSB MISO (OUTPUT) CPHA=1 MOSI (INPUT) MSB tSSPID MSB VALID tHSPID tSSPID tHSPID LSB VALID tDSOE MISO (OUTPUT) CPHA=0 MOSI (INPUT) tDDSPID MSB LSB tDSDHI tHSPID tSSPID MSB VALID LSB VALID Figure 22. Serial Peripheral Interface (SPI) Port--Slave Timing Rev. B | Page 36 of 64 | June 2007 ADSP-BF561 Universal Asynchronous Receiver Transmitter (UART) Port--Receive and Transmit Timing Figure 23 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 23, there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. CLKOUT (SAMPLE CLOCK) Rx DATA8-5 STOP RECEIVE INTERNAL UART RECEIVE INTERRUPT UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ START Tx AS DATA WRITEN TO BUFFER INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT DATA8-5 STOP2-1 TRANSMIT Figure 23. UART Port--Receive and Transmit Timing Rev. B | Page 37 of 64 | June 2007 ADSP-BF561 Programmable Flags Cycle Timing Table 28 and Figure 24 describe programmable flag operations. Table 28. Programmable Flags Cycle Timing Parameter Timing Requirement tWFI Flag Input Pulse Width Switching Characteristic tDFO Flag Output Delay from CLKOUT Low Min tSCLK + 1 6 Max Unit ns ns CLKOUT tDFO PFx (OUTPUT) FLAG OUTPUT tWFI PFx (INPUT) FLAG INPUT Figure 24. Programmable Flags Cycle Timing Rev. B | Page 38 of 64 | June 2007 ADSP-BF561 Timer Cycle Timing Table 29 and Figure 25 describe timer expired operations. The input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency of fSCLK/2 MHz. Table 29. Timer Cycle Timing Parameter Timing Characteristics Timer Pulse Width Input Low1 (Measured in SCLK Cycles) tWL tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles) Switching Characteristic tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles) 1 2 Min 1 1 1 Max Unit SCLK SCLK (232-1) SCLK The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPIxCLK input pins in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles. CLKOUT tHTO TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) tWL tWH Figure 25. Timer PWM_OUT Cycle Timing Rev. B | Page 39 of 64 | June 2007 ADSP-BF561 JTAG Test and Emulation Port Timing Table 30 and Figure 26 describe JTAG port operations. Table 30. JTAG Port Timing Parameter Timing Parameters tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK High1 tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulse Width2 (Measured in TCK Cycles) Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low3 1 Min 20 4 4 4 5 4 Max Unit ns ns ns ns ns TCK 0 10 12 ns ns System Inputs= DATA31-0, ARDY, PF47-0, PPI0CLK, PPI1CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX, RESET, NMI0, NMI1, BMODE1-0, BR, and PPIxD7-0. 2 50 MHz maximum 3 System Outputs = DATA31-0, ADDR25-2, ABE3-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3-0, PF47-0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, and PPIxD7-0. tTCK TCK tSTAP TMS TDI tHTAP tDTDO TDO tSSYS SYSTEM INPUTS tHSYS tDSYS SYSTEM OUTPUTS Figure 26. JTAG Port Timing Rev. B | Page 40 of 64 | June 2007 ADSP-BF561 OUTPUT DRIVE CURRENTS Figure 27 through Figure 34 on Page 42 show typical current voltage characteristics for the output drivers of the ADSP-BF561 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Refer to Table 8 on Page 17 to identify the driver type for a pin. 150 VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V 150 VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V 100 SOURCE CURRENT (mA) 50 0 VOH -50 100 SOURCE CURRENT (mA) -100 50 -150 0 VOH VOL 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) -50 VOL 150 Figure 29. Drive Current B (Low VDDEXT) -100 VDDEXT = 3.65V VDDEXT = 2.95V VDDEXT = 3.30V -150 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE CURRENT (mA) 100 SOURCE VOLTAGE (V) Figure 27. Drive Current A (Low VDDEXT) 150 VDDEXT = 3.65V VDDEXT = 3.30V VDDEXT = 2.95V 50 0 VOH -50 100 SOURCE CURRENT (mA) -100 50 -150 0 VOH -50 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3.5 VOL Figure 30. Drive Current B (High VDDEXT) -100 VOL 60 VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V -150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 SOURCE VOLTAGE (V) 20 SOURCE CURRENT (mA) Figure 28. Drive Current A (High VDDEXT) 0 VOH -20 -40 VOL -60 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 31. Drive Current C (Low VDDEXT) Rev. B | Page 41 of 64 | June 2007 ADSP-BF561 100 80 60 SOURCE CURRENT (mA) 40 20 0 VOH -20 -40 -60 -80 -100 0 VOL VDDEXT = 3.65V VDDEXT = 3.30V VDDEXT = 2.95V POWER DISSIPATION Many operating conditions can affect power dissipation. System designers should refer to Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)--use site search on "EE-293." This document provides detailed information for optimizing your design for lowest power. See the ADSP-BF561 Blackfin Processor Hardware Reference Manual for definitions of the various operating modes and for instructions on how to minimize system power. TEST CONDITIONS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 35 shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is 1.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. INPUT OR OUTPUT 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Figure 32. Drive Current C (High VDDEXT) 100 80 60 SOURCE CURRENT (mA) 40 20 0 -20 -40 -60 -80 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 VOL VOH VDDEXT = 2.75V VDDEXT = 2.50V VDDEXT = 2.25V VMEAS VMEAS Figure 35. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time Measurement Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 36 on Page 43. The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for VDDEXT (nominal) = 2.5 V/3.3 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED - t TRIP SOURCE VOLTAGE (V) Figure 33. Drive Current D (Low VDDEXT) 150 VDDEXT = 3.65V VDDEXT = 3.30V VDDEXT = 2.95V 100 SOURCE CURRENT (mA) 50 0 VOH If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. -50 VOL -100 Output Disable Time Measurement Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 36 on Page 43. t DIS = t DIS_MEASURED - t DECAY -150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3.5 Figure 34. Drive Current D (High VDDEXT) Rev. B | Page 42 of 64 | June 2007 ADSP-BF561 RISE AND FALL TIME ns (10% to 90%) The time for the voltage on the bus to decay by V is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: t DECAY = ( C L V ) I L The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. The time tDIS_MEASURED is the interval from when the reference signal switches, to when the output voltage decays V from the measured output high or output low voltage. 14 12 RISE TIME 10 8 FALL TIME 6 4 Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF561 processor's output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on Page 22 (for example tDSDAT for an SDRAM write cycle as shown in SDRAM Interface Timing on Page 26). 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 38. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver A at VDDEXT (min) 12 RISE AND FALL TIME ns (10% to 90%) 10 RISE TIME 8 FALL TIME 6 REFERENCE SIGNAL tDIS_MEASURED tDIS VOH (MEASURED) VOL (MEASURED) tENA_MEASURED tENA VOH(MEASURED) 4 2 VOH (MEASURED) V VOL (MEASURED) + V VTRIP(HIGH) VTRIP(LOW) VOL(MEASURED) 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 tDECAY tTRIP Figure 39. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver A at VDDEXT (max) 12 RISE AND FALL TIME ns (10% to 90%) OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE Figure 36. Output Enable/Disable 10 RISE TIME 8 FALL TIME Capacitive Loading Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 37). VLOAD is 1.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. Figure 38 through Figure 45 on Page 44 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. TO OUTPUT PIN 30pF 50 VLOAD 6 4 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver B at VDDEXT (min) Figure 37. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Rev. B | Page 43 of 64 | June 2007 ADSP-BF561 DDEXT 10 RISE AND FALL TIME ns (10% to 90%) 9 8 RISE TIME 7 6 FALL TIME 5 4 3 2 1 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 RISE AND FALL TIME ns (10% to 90%) 18 16 14 RISE TIME 12 10 FALL TIME 8 6 4 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver B at VDDEXT (max) 30 RISE AND FALL TIME ns (10% to 90%) Figure 44. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver D at VDDEXT (min) 14 RISE AND FALL TIME ns (10% to 90%) 12 10 RISE TIME 25 RISE TIME 20 8 FALL TIME 6 4 2 15 FALL TIME 10 5 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver C at VDDEXT (min) 20 RISE AND FALL TIME ns (10% to 90%) 18 16 RISE TIME 14 12 FALL TIME 10 8 6 4 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver D at VDDEXT (max) ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( JT x P D ) where: TJ = junction temperature ( C). TCASE = case temperature ( C) measured by customer at top center of package. JT = from Table 31 on Page 45 through Table 33 on Page 45. PD = power dissipation (see Power Dissipation on Page 42 for the method to calculate PD). Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + ( JA x P D ) where: TA = ambient temperature ( C). Figure 43. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver C at VDDEXT (max) Rev. B | Page 44 of 64 | June 2007 ADSP-BF561 In Table 31 through Table 33, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Thermal resistance JA in Table 31 through Table 33 is the figure of merit relating to performance of the package and board in a convective environment. JMA represents the thermal resistance under two conditions of airflow. JB represents the heat extracted from the periphery of the board. JT represents the correlation between TJ and TCASE. Values of JB are provided for package comparison and printed circuit board design considerations. Table 31. Thermal Characteristics for BC-256-4 (17 mm x 17 mm) Package Parameter JA JMA JMA JC JT JT JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Typical 18.1 15.9 15.1 3.72 0.11 0.18 0.18 Unit C/W C/W C/W C/W C/W C/W C/W Table 32. Thermal Characteristics for BC-256-1 (12 mm x 12 mm) Package Parameter JA JMA JMA JB JC JT JT JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable Not Applicable 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Typical 25.6 22.4 21.6 18.9 4.85 0.15 n/a n/a Unit C/W C/W C/W C/W C/W C/W C/W C/W Table 33. Thermal Characteristics for B-297 Package Parameter JA JMA JMA JB JC JT JT JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable Not Applicable 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Typical 20.6 17.8 17.4 16.3 7.15 0.37 n/a n/a Unit C/W C/W C/W C/W C/W C/W C/W C/W Rev. B | Page 45 of 64 | June 2007 ADSP-BF561 256-BALL CSP_BGA (17 mm 17 mm) BALL ASSIGNMENT Table 34 lists the 256-Ball CSP_BGA (17 mm 17 mm) ball assignment by ball number. Table 35 on Page 48 lists the ball assignment alphabetically by signal. Table 34. 256-Ball CSP_BGA (17 mm Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 Signal VDDEXT ADDR22 ADDR18 ADDR14 ADDR11 AMS3 AMS0 ARDY SMS2 SCLK0 SCLK1 ABE2 ABE3 ADDR06 ADDR03 VDDEXT ADDR24 ADDR23 ADDR19 ADDR17 ADDR12 ADDR10 AMS1 AOE SMS1 SCKE BR BG ADDR08 ADDR05 ADDR02 DATA04 PPI0SYNC1 ADDR25 PPI0CLK ADDR20 ADDR16 ADDR13 AMS2 ARE Ball No. C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 17 mm) Ball Assignment (Numerically by Ball Number) Signal SMS3 SWE SA10 ABE0 ADDR07 ADDR04 DATA0 DATA05 PPI0D15 PPI0SYNC3 PPI0SYNC2 ADDR21 ADDR15 ADDR09 AWE SMS0 SRAS SCAS BGH ABE1 DATA02 DATA01 DATA03 DATA07 PPI0D11 PPI0D13 PPI0D12 PPI0D14 PPI1CLK VDDINT GND VDDINT GND VDDINT GND VDDINT DATA06 DATA13 DATA09 DATA12 Ball No. F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 Signal CLKIN PPI0D10 RESET BYPASS VDDEXT VDDEXT VDDEXT GND GND VDDEXT VDDEXT VDDEXT DATA11 DATA08 DATA10 DATA16 XTAL VDDEXT VDDEXT GND GND VDDEXT GND GND GND GND VDDEXT VDDEXT DATA17 DATA14 DATA15 DATA18 VROUT0 GND GND VDDINT VDDINT GND GND GND Ball No. H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 Signal GND GND GND GND GND DATA21 DATA19 DATA23 VROUT1 PPI0D8 PPI0D7 PPI0D9 GND GND GND GND GND GND GND VDDINT VDDINT DATA20 DATA22 DATA24 PPI0D6 PPI0D5 PPI0D4 PPI1SYNC3 VDDEXT VDDEXT GND GND GND GND VDDEXT GND GND DATA26 DATA25 DATA27 Ball No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 Signal PPI0D3 PPI0D2 PPI0D1 PPI0D0 VDDEXT VDDEXT VDDEXT VDDEXT GND VDDEXT VDDEXT VDDEXT NC DT0PRI DATA31 DATA28 PPI1SYNC2 PPI1D15 PPI1D14 PPI1D9 VDDINT VDDINT GND VDDINT GND VDDINT GND VDDINT RSCLK0 DR0PRI TSCLK0 DATA29 PPI1SYNC1 PPI1D10 PPI1D7 PPI1D5 PF0 PF04 PF09 PF12 Rev. B | Page 46 of 64 | June 2007 ADSP-BF561 Table 34. 256-Ball CSP_BGA (17 mm Ball No. N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 Signal GND BMODE1 BMODE0 RX DR1SEC DT1SEC RFS0 DATA30 PPI1D13 PPI1D8 PPI1D6 PPI1D0 Ball No. P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 17 mm) Ball Assignment (Numerically by Ball Number) (Continued) Signal PF01 PF06 PF08 PF15 NMI1 TMS NMI0 SCK RFS1 TFS1 DR0SEC DT0SEC Ball No. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Signal PPI1D12 PPI1D11 PPI1D4 PPI1D1 PF02 PF07 PF11 PF14 TCK TRST SLEEP MOSI Ball No. R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 Signal RSCLK1 TSCLK1 NC TFS0 VDDEXT NC PPI1D3 PPI1D2 PF03 PF05 PF10 PF13 Ball No. T9 T10 T11 T12 T13 T14 T15 T16 Signal TDO TDI EMU MISO TX DR1PRI DT1PRI VDDEXT Rev. B | Page 47 of 64 | June 2007 ADSP-BF561 Table 35. 256-Ball CSP_BGA (12 mm Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No. C12 D12 A12 A13 B15 A15 C14 B14 A14 C13 B13 D6 B6 A5 B5 C6 A4 D5 C5 B4 A3 B3 C4 D4 A2 B2 B1 C2 A7 B7 C7 A6 B8 A8 C8 D7 B12 D11 N11 N10 Signal BR BYPASS CLKIN DATA0 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI 12 mm) Ball Assignment (Alphabetically by Signal) Ball No. B11 F4 F1 C15 D14 D13 D15 B16 C16 E13 D16 F14 E15 F15 F13 E16 E14 G14 G15 F16 G13 G16 H15 J14 H14 J15 H16 J16 K15 K14 K16 L16 M16 N16 L15 M14 P15 T14 N13 L14 Signal DT0SEC DT1PRI DT1SEC EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. P16 T15 N14 T11 E7 E9 E11 F8 F9 G4 G5 G7 G8 G9 G10 H2 H3 H6 H7 H8 H9 H10 H11 H12 H13 J5 J6 J7 J8 J9 J10 J11 K7 K8 K9 K10 K12 K13 L9 M7 Signal GND GND GND MISO MOSI NC NC NC NMI0 NMI1 PF0 PF01 PF02 PF03 PF04 PF05 PF06 PF07 PF08 PF09 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 PPI0D12 Ball No. M9 M11 N9 T12 R12 L13 R15 T2 P11 P9 N5 P5 R5 T5 N6 T6 P6 R6 P7 N7 T7 R7 N8 T8 R8 P8 C3 L4 L3 L2 L1 K3 K2 K1 J3 J2 J4 F2 E1 E3 Signal PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RX SA10 SCAS SCK SCKE SCLK0 SCLK1 SLEEP SMS0 Ball No. E2 E4 D1 C1 D3 D2 E5 P4 R4 T4 T3 R3 N4 P3 N3 P2 M4 N2 R2 R1 P1 M3 M2 N1 M1 K4 F3 N15 P13 M13 R13 N12 C11 D10 P12 B10 A10 A11 R11 D8 Rev. B | Page 48 of 64 | June 2007 ADSP-BF561 Table 35. 256-Ball CSP_BGA (12 mm Signal SMS1 SMS2 SMS3 SRAS SWE TCK TDI TDO TFS0 TFS1 TMS TRST Ball No. B9 A9 C9 D9 C10 R9 T10 T9 R16 P14 P10 R10 Signal TSCLK0 TSCLK1 TX VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT 12 mm) Ball Assignment (Alphabetically by Signal) (Continued) Ball No. M15 R14 T13 A1 A16 F5 F6 F7 F10 F11 F12 G2 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. G3 G6 G11 G12 K5 K6 K11 L5 L6 L7 L8 L10 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT Ball No. L11 L12 T1 T16 E6 E8 E10 E12 H4 H5 J12 J13 Signal VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball No. M5 M6 M8 M10 M12 H1 J1 G1 Rev. B | Page 49 of 64 | June 2007 ADSP-BF561 Figure 46 lists the top view of the 256-Ball CSP_BGA (17 mm x 17 mm) ball configuration. Figure 47 lists the bottom view. A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 1 2 3 4 5 6 7 8 TOP VIEW 9 10 11 12 13 14 15 16 Figure 46. 256-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 16 15 14 13 12 11 10 9 8 7 BOTTOM VIEW 6 5 4 3 2 1 Figure 47. 256-Ball CSP_BGA Ball Configuration (Bottom View) Rev. B | Page 50 of 64 | June 2007 ADSP-BF561 256-BALL CSP_BGA (12 mm 12 mm) BALL ASSIGNMENT Table 36 lists the 256-Ball CSP_BGA (12 mm 12 mm) ball assignment by ball number. Table 37 on Page 53 lists the ball assignment alphabetically by signal. Table 36. 256-Ball CSP_BGA (12 mm Ball No. Signal A01 VDDEXT A02 ADDR24 A03 ADDR20 A04 VDDEXT A05 ADDR14 A06 ADDR10 A07 AMS3 A08 AWE A09 VDDEXT A10 SMS3 A11 SCLK0 A12 SCLK1 A13 BG A14 ABE2 A15 ABE3 A16 VDDEXT B01 PPI1CLK B02 ADDR22 B03 ADDR18 B04 ADDR16 B05 ADDR12 B06 VDDEXT B07 AMS1 B08 ARE B09 SMS1 B10 SCKE B11 VDDEXT B12 BR B13 ABE1 B14 ADDR06 B15 ADDR04 B16 DATA0 C01 PPI0SYNC2 C02 PPI0CLK C03 ADDR25 C04 ADDR19 C05 GND C06 ADDR11 C07 AOE C08 AMS0 12 mm) Ball Assignment (Numerically by Ball Number) Ball No. Signal F01 CLKIN F02 VDDEXT F03 RESET F04 PPI0D10 F05 ADDR21 F06 ADDR17 F07 VDDINT F08 GND F09 VDDINT F10 GND F11 ADDR08 F12 DATA10 F13 DATA8 F14 DATA12 F15 DATA9 F16 DATA11 G01 XTAL G02 GND G03 VDDEXT G04 BYPASS G05 PPI0D14 G06 GND G07 GND G08 GND G09 VDDINT G10 ADDR05 G11 ADDR03 G12 DATA15 G13 DATA14 G14 GND G15 DATA13 G16 VDDEXT H01 GND H02 GND H03 PPI0D9 H04 PPI0D7 H05 PPI0D5 H06 VDDINT H07 VDDINT H08 GND Ball No. Signal H09 GND H10 GND H11 VDDINT H12 DATA16 H13 DATA18 H14 DATA20 H15 DATA17 H16 DATA19 J01 VROUT0 J02 VROUT1 J03 PPI0D2 J04 PPI0D3 J05 PPI0D1 J06 VDDEXT J07 GND J08 VDDINT J09 VDDINT J10 VDDINT J11 GND J12 DATA30 J13 DATA22 J14 GND J15 DATA21 J16 DATA23 K01 PPI0D6 K02 PPI0D4 K03 PPI0D8 K04 PPI1SYNC1 K05 PPI1D14 K06 VDDEXT K07 GND K08 VDDINT K09 GND K10 GND K11 VDDINT K12 DATA28 K13 DATA26 K14 DATA24 K15 DATA25 K16 VDDEXT Ball No. Signal L01 PPI0D0 L02 PPI1SYNC2 L03 GND L04 PPI1SYNC3 L05 VDDEXT L06 PPI1D11 L07 GND L08 VDDINT L09 GND L10 VDDEXT L11 GND L12 DR0PRI L13 TFS0 L14 GND L15 DATA27 L16 DATA29 M01 PPI1D15 M02 PPI1D13 M03 PPI1D9 M04 GND M05 NC M06 PF3 M07 PF7 M08 VDDINT M09 GND M10 BMODE0 M11 SCK M12 DR1PRI M13 NC M14 VDDEXT M15 DATA31 M16 DT0PRI N01 PPI1D12 N02 PPI1D10 N03 PPI1D3 N04 PPI1D1 N05 PF1 N06 PF9 N07 GND N08 PF13 Ball No. Signal C09 SMS2 C10 SRAS C11 GND C12 BGH C13 GND C14 ADDR07 C15 DATA1 C16 DATA3 D01 PPI0D13 D02 PPI0D15 D03 PPI0SYNC3 D04 ADDR23 D05 GND D06 GND D07 ADDR09 D08 GND D09 ARDY D10 SCAS D11 SA10 D12 VDDEXT D13 ADDR02 D14 GND D15 DATA5 D16 DATA6 E01 GND E02 PPI0D11 E03 PPI0D12 E04 PPI0SYNC1 E05 ADDR15 E06 ADDR13 E07 AMS2 E08 VDDINT E09 SMS0 E10 SWE E11 ABE0 E12 DATA2 E13 GND E14 DATA4 E15 DATA7 E16 VDDEXT Rev. B | Page 51 of 64 | June 2007 ADSP-BF561 Table 36. 256-Ball CSP_BGA (12 mm Ball No. Signal N09 TDO N10 BMODE1 N11 MOSI N12 GND N13 RFS1 N14 GND N15 DT0SEC N16 TSCLK0 P01 PPI1D8 P02 GND P03 PPI1D5 P04 PF0 12 mm) Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal R01 PPI1D7 R02 PPI1D6 R03 PPI1D2 R04 PPI1D0 R05 PF4 R06 PF8 R07 PF10 R08 PF14 R09 NMI1 R10 TDI R11 EMU R12 MISO Ball No. Signal R13 TX/PF26 R14 TSCLK1 R15 DT1PRI R16 RFS0 T01 VDDEXT T02 PPI1D4 T03 VDDEXT T04 PF2 T05 PF6 T06 VDDEXT T07 PF12 T08 VDDEXT Ball No. Signal T09 TCK T10 TMS T11 SLEEP T12 VDDEXT T13 RX/PF27 T14 DR1SEC T15 DT1SEC T16 VDDEXT Ball No. Signal P05 GND P06 PF5 P07 PF11 P08 PF15 P09 GND P10 TRST P11 NMI0 P12 GND P13 RSCLK1 P14 TFS1 P15 RSCLK0 P16 DR0SEC Rev. B | Page 52 of 64 | June 2007 ADSP-BF561 Table 37. 256-Ball CSP_BGA (12 mm Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No. E11 B13 A14 A15 D13 G11 B15 G10 B14 C14 F11 D07 A06 C06 B05 E06 A05 E05 B04 F06 B03 C04 A03 F05 B02 D04 A02 C03 C08 B07 E07 A07 C07 D09 B08 A08 A13 C12 M10 N10 12 mm) Ball Assignment (Alphabetically by Signal) Ball No. B12 G04 F01 B16 C15 E12 C16 E14 D15 D16 E15 F13 F15 F12 F16 F14 G15 G13 G12 H12 H15 H13 H16 H14 J15 J13 J16 K14 K15 K13 L15 K12 L16 J12 M15 L12 P16 M12 T14 M16 Signal DT0SEC DT1PRI DT1SEC EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. N15 R15 T15 R11 C05 C11 C13 D05 D06 D08 D14 E01 E13 F08 F10 G02 G06 G07 G08 G14 H01 H02 H08 H09 H10 J07 J11 J14 K07 K09 K10 L03 L07 L09 L11 L14 M04 M09 N07 N12 Signal GND GND GND GND GND MISO MOSI NC NC NMI0 NMI1 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 Ball No. N14 P02 P05 P09 P12 R12 N11 M05 M13 P11 R09 P04 N05 T04 M06 R05 P06 T05 M07 R06 N06 R07 P07 T07 N08 R08 P08 C02 L01 J05 J03 J04 K02 H05 K01 H04 K03 H03 F04 E02 Signal BR BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI Rev. B | Page 53 of 64 | June 2007 ADSP-BF561 Table 37. 256-Ball CSP_BGA (12 mm Signal PPI0D12 PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 Ball No. E03 D01 G05 D02 E04 C01 D03 B01 R04 N04 R03 N03 T02 P03 R02 R01 P01 M03 N02 L06 N01 M02 K05 M01 12 mm) Ball Assignment (Alphabetically by Signal) (Continued) Ball No. K04 L02 L04 F03 R16 N13 P15 P13 T13 D11 D10 M11 B10 A11 A12 T11 E09 B09 C09 A10 C10 E10 T09 R10 Signal TDO TFS0 TFS1 TMS TRST TSCLK0 TSCLK1 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. N09 L13 P14 T10 P10 N16 R14 R13 A01 A04 A09 A16 B06 B11 D12 E16 F02 G03 G16 J06 K06 K16 L05 L10 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball No. M14 T01 T03 T06 T08 T12 T16 E08 F07 F09 G09 H06 H07 H11 J08 J09 J10 K08 K11 L08 M08 J01 J02 G01 Signal PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RX SA10 SCAS SCK SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS SWE TCK TDI Rev. B | Page 54 of 64 | June 2007 ADSP-BF561 Figure 48 lists the top view of the 256-Ball CSP_BGA (12 mm 12 mm) ball configuration. Figure 49 lists the bottom view. A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 1 2 3 4 5 6 7 8 TOP VIEW 9 10 11 12 13 14 15 16 Figure 48. 256-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 16 15 14 13 12 11 10 9 8 7 BOTTOM VIEW 6 5 4 3 2 1 Figure 49. 256-Ball CSP_BGA Ball Configuration (Bottom View) Rev. B | Page 55 of 64 | June 2007 ADSP-BF561 297-BALL PBGA BALL ASSIGNMENT Table 38 lists the 297-Ball PBGA ball assignment numerically by ball number. Table 39 on Page 58 lists the ball assignment alphabetically by signal. Table 38. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 Signal GND ADDR25 ADDR23 ADDR21 ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR09 AMS3 AMS1 AWE ARE SMS0 SMS2 SRAS SCAS SCLK0 SCLK1 BGH ABE0 ABE2 ADDR08 ADDR06 GND PPI1CLK GND ADDR24 ADDR22 ADDR20 ADDR18 ADDR16 ADDR14 ADDR12 ADDR10 AMS2 AMS0 AOE ARDY Ball No. B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C01 C02 C03 C04 C05 C22 C23 C24 C25 C26 D01 D02 D03 D04 D23 D24 D25 D26 E01 E02 E03 E24 E25 E26 F01 F02 F25 F26 Signal SMS1 SMS3 SCKE SWE SA10 BR BG ABE1 ABE3 ADDR07 GND ADDR05 PPI0SYNC3 PPI0CLK GND GND GND GND GND GND ADDR04 ADDR03 PPI0SYNC1 PPI0SYNC2 GND GND GND GND ADDR02 DATA1 PPI0D15 PPI0D14 GND GND DATA0 DATA3 PPI0D13 PPI0D12 DATA2 DATA5 Ball No. G01 G02 G25 G26 H01 H02 H25 H26 J01 J02 J10 J11 J12 J13 J14 J15 J16 J17 J18 J25 J26 K01 K02 K10 K11 K12 K13 K14 K15 K16 K17 K18 K25 K26 L01 L02 L10 L11 L12 L13 Signal PPI0D11 PPI0D10 DATA4 DATA7 BYPASS RESET DATA6 DATA9 CLKIN GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA8 DATA11 XTAL NC VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA10 DATA13 NC NC VDDEXT GND GND GND Ball No. L14 L15 L16 L17 L18 L25 L26 M01 M02 M10 M11 M12 M13 M14 M15 M16 M17 M18 M25 M26 N01 N02 N10 N11 N12 N13 N14 N15 N16 N17 N18 N25 N26 P01 P02 P10 P11 P12 P13 P14 Signal GND GND GND GND VDDINT DATA12 DATA15 VROUT0 GND VDDEXT GND GND GND GND GND GND GND VDDINT DATA14 DATA17 VROUT1 PPI0D9 VDDEXT GND GND GND GND GND GND GND VDDINT DATA16 DATA19 PPI0D7 PPI0D8 VDDEXT GND GND GND GND Rev. B | Page 56 of 64 | June 2007 ADSP-BF561 Table 38. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. P15 P16 P17 P18 P25 P26 R01 R02 R10 R11 R12 R13 R14 R15 R16 R17 R18 R25 R26 T01 T02 T10 T11 T12 T13 T14 T15 T16 T17 T18 T25 T26 U01 U02 U10 Signal GND GND GND VDDINT DATA18 DATA21 PPI0D5 PPI0D6 VDDEXT GND GND GND GND GND GND GND VDDINT DATA20 DATA23 PPI0D3 PPI0D4 VDDEXT GND GND GND GND GND GND GND VDDINT DATA22 DATA25 PPI0D1 PPI0D2 VDDEXT Ball No. U11 U12 U13 U14 U15 U16 U17 U18 U25 U26 V01 V02 V25 V26 W01 W02 W25 W26 Y01 Y02 Y25 Y26 AA01 AA02 AA25 AA26 AB01 AB02 AB03 AB24 AB25 AB26 AC01 AC02 AC03 Signal VDDEXT VDDEXT VDDEXT GND VDDINT VDDINT VDDINT VDDINT DATA24 DATA27 PPI1SYNC3 PPI0D0 DATA26 DATA29 PPI1SYNC1 PPI1SYNC2 DATA28 DATA31 PPI1D15 PPI1D14 DATA30 DT0PRI PPI1D13 PPI1D12 DT0SEC TSCLK0 PPI1D11 PPI1D10 GND GND TFS0 DR0PRI PPI1D9 PPI1D8 GND Ball No. AC04 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 Signal GND GND GND DR0SEC RFS0 PPI1D7 PPI1D6 GND GND GND GND GND GND NC RSCLK0 PPI1D5 GND PPI1D3 PPI1D1 PF0 PF2 PF4 PF6 PF8 PF10 PF12 PF14 NC TDO TRST EMU BMODE1 BMODE0 MISO MOSI Ball No. AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal RX RFS1 DR1SEC TFS1 GND NC GND PPI1D4 PPI1D2 PPI1D0 PF1 PF3 PF5 PF7 PF9 PF11 PF13 PF15 NMI1 TCK TDI TMS SLEEP NMI0 SCK TX RSCLK1 DR1PRI TSCLK1 DT1SEC DT1PRI GND Rev. B | Page 57 of 64 | June 2007 ADSP-BF561 Table 39. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No. A22 B22 A23 B23 D25 C26 C25 B26 A25 B24 A24 A10 B10 A09 B09 A08 B08 A07 B07 A06 B06 A05 B05 A04 B04 A03 B03 A02 B12 A12 B11 A11 B13 B14 A14 A13 B21 A21 AE18 AE17 Signal BR BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI Ball No. B20 H01 J01 E25 D26 F25 E26 G25 F26 H25 G26 J25 H26 K25 J26 L25 K26 M25 L26 N25 M26 P25 N26 R25 P26 T25 R26 U25 T26 V25 U26 W25 V26 Y25 W26 AB26 AC25 AF22 AE23 Y26 Signal DT0SEC DT1PRI DT1SEC EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. AA25 AF25 AF24 AE16 A01 A26 B02 B25 C03 C04 C05 C22 C23 C24 D03 D04 D23 D24 E03 E24 J02 L11 L12 L13 L14 L15 L16 L17 M02 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13 N14 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. N15 N16 N17 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R17 T11 T12 T13 T14 T15 T16 T17 U14 AB03 AB24 AC03 AC04 AC23 AC24 AD03 AD04 AD05 AD22 AD23 AD24 AE02 AE25 AF01 Rev. B | Page 58 of 64 | June 2007 ADSP-BF561 Table 39. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued) Signal GND MISO MOSI NC NC NC NC NC NC NMI0 NMI1 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 Ball No. AF26 AE19 AE20 K02 L01 L02 AD25 AE13 AE26 AF18 AF13 AE05 AF05 AE06 AF06 AE07 AF07 AE08 AF08 AE09 AF09 AE10 AF10 AE11 AF11 AE12 AF12 C02 V02 U01 U02 T01 T02 R01 R02 Signal PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 PPI0D12 PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 Ball No. P01 P02 N02 G02 G01 F02 F01 E02 E01 D01 D02 C01 B01 AF04 AE04 AF03 AE03 AF02 AE01 AD02 AD01 AC02 AC01 AB02 AB01 AA02 AA01 Y02 Y01 W01 W02 V01 H02 AC26 AE22 Signal RSCLK0 RSCLK1 RX SA10 SCAS SCK SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS SWE TCK TDI TDO TFS0 TFS1 TMS TRST TSCLK0 TSCLK1 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. AD26 AF21 AE21 B19 A18 AF19 B17 A19 A20 AF17 A15 B15 A16 B16 A17 B18 AF14 AF15 AE14 AB25 AE24 AF16 AE15 AA26 AF23 AF20 J10 J11 J12 J13 J14 J15 K10 K11 K12 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball No. K13 K14 K15 L10 M10 N10 P10 R10 T10 U10 U11 U12 U13 J16 J17 J18 K16 K17 K18 L18 M18 N18 P18 R18 T18 U15 U16 U17 U18 M01 N01 K01 Rev. B | Page 59 of 64 | June 2007 ADSP-BF561 Figure 50 lists the top view of the 297-Ball PBGA ball configuration. Figure 51 lists the bottom view. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 KEY: VDDINT VDDEXT GND I/O NC VROUT TOP VIEW Figure 50. 297-Ball PBGA Ball Configuration (Top View) A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KEY: VDDINT VDDEXT GND I/O NC VROUT BOTTOM VIEW Figure 51. 297-Ball PBGA Ball Configuration (Bottom View) Rev. B | Page 60 of 64 | June 2007 ADSP-BF561 OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 256-BALL CSP_BGA (BC-256-4) 17.00 BSC SQ 15.00 BSC SQ 1.00 BSC BALL PITCH CL A1 BALL PAD CORNER A1 BALL PAD CORNER A B C D E F G H J K L M N CL P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW BOTTOM VIEW 1.90 1.76 1.61 SIDE VIEW 0.45 MIN DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-192-AAF-1, WITH EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.45 0.20 MAX COPLANARITY SEATING PLANE DETAIL A 0.70 BALL DIAMETER 0.60 0.50 Figure 52. 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-4) Rev. B | Page 61 of 64 | June 2007 ADSP-BF561 12.00 BSC SQ 0.65 BSC BALL PITCH A1 BALL PAD CORNER A B C D E F G H J K L M N P R T 9.75 BSC SQ CL A1 BALL PAD CORNER CL TOP VIEW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 1.70 1.51 1.36 SIDE VIEW 0.25 MIN DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.25 0.10 MAX COPLANARITY 0.45 BALL DIAMETER 0.40 0.35 SEATING PLANE DETAIL A Figure 53. 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-1) Rev. B | Page 62 of 64 | June 2007 ADSP-BF561 27.00 BSC SQ 1.00 BSC BALL PITCH A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25.00 BSC SQ 8.00 CL A1 BALL PAD CORNER 8.00 CL TOP VIEW 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 2.43 2.23 2.03 SIDE VIEW 0.40 MIN DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAL-1. 3. MINIMUM BALL HEIGHT 0.40 0.20 MAX COPLANARITY SEATING PLANE DETAIL A 0.70 BALL DIAMETER 0.60 0.50 Figure 54. 297-Ball Plastic Ball Grid Array (PBGA) (B-297) SURFACE MOUNT DESIGN Table 40 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 40. BGA Data for Use with Surface Mount Design Package 256-Ball CSP_BGA (BC-256-1) 256-Ball CSP_BGA (BC-256-4) 297-Ball PBGA (B-297) Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.30 mm diameter 0.43 mm diameter 0.43 mm diameter Ball Pad Size 0.43 mm diameter 0.55 mm diameter 0.58 mm diameter Rev. B | Page 63 of 64 | June 2007 ADSP-BF561 ORDERING GUIDE Temperature Speed Grade Operating Voltage Range1 Rate (Max) (Nom) Package Description 0C to +70C 600 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) 0 C to +70C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) 0C to +70C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) 0C to +70C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) -40C to +85C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) -40C to +85C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) -40C to +85C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) -40C to +85C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) -40C to +85C 533 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 297-Ball Plastic Ball Grid Array (PBGA) 0C to +70C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 600 MHz 1.35 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 533 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) Package Option BC-256-1 BC-256-1 B-297 B-297 B-297 B-297 B-297 B-297 B-297 B-297 B-297 BC-256-4 BC-256-4 BC-256-4 BC-256-4 BC-256-4 Model ADSP-BF561SKBCZ6002 ADSP-BF561SKBCZ5002 ADSP-BF561SKB500 ADSP-BF561SKB600 ADSP-BF561SKBZ5002 ADSP-BF561SKBZ6002 ADSP-BF561SBB600 ADSP-BF561SBB500 ADSP-BF561SBBZ6002 ADSP-BF561SBBZ5002 ADSP-BF561WBBZ-5A2, 3 ADSP-BF561SKBCZ-6A2 ADSP-BF561SKBCZ-5A2 ADSP-BF561SBBCZ-6A2 ADSP-BF561SBBCZ-5A2 ADSP-BF561WBBCZ-5A2, 3 1 2 Referenced temperature is ambient temperature. Z = RoHS compliant part. 3 W indicates automotive grade part. The internal voltage regulation feature is not available on automotive parts. (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04696-0-6/07(B) Rev. B | Page 64 of 64 | June 2007 |
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